imx: consolidate set_chipselect_size function

Move MX5 specific set_chipselect_size function into generic i.MX part,
such that MX6 based boards are able to use this function as well.

While doing this the iomuxc gpr member needed to be consolidated between
MX5 and MX6.

Signed-off-by: Fabio Estevam <[email protected]>

diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c
index 2d53669c89d58221cc40cf83ff55373345134563..3753c14df3977c7b70459d5db2e3df0a05791f95 100644 (file)
--- a/arch/arm/cpu/armv7/mx5/soc.c
+++ b/arch/arm/cpu/armv7/mx5/soc.c
@@ -85,37 +85,6 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 }
 #endif
 
-void set_chipselect_size(int const cs_size)
-{
-       unsigned int reg;
-       struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
-       reg = readl(&iomuxc_regs->gpr1);
-
-       switch (cs_size) {
-       case CS0_128:
-               reg &= ~0x7;    /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
-               reg |= 0x5;
-               break;
-       case CS0_64M_CS1_64M:
-               reg &= ~0x3F;   /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
-               reg |= 0x1B;
-               break;
-       case CS0_64M_CS1_32M_CS2_32M:
-               reg &= ~0x1FF;  /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
-               reg |= 0x4B;
-               break;
-       case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
-               reg &= ~0xFFF;  /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
-               reg |= 0x249;
-               break;
-       default:
-               printf("Unknown chip select size: %d\n", cs_size);
-               break;
-       }
-
-       writel(reg, &iomuxc_regs->gpr1);
-}
-
 #ifdef CONFIG_MX53
 void boot_mode_apply(unsigned cfg_val)
 {

diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index 09fc22760d0c6e973359f121f92c63feed26793d..24740b860397a22049c975aa98d6b73e25397222 100644 (file)
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -187,3 +187,34 @@ void arch_preboot_os(void)
        ipuv3_fb_shutdown();
 }
 #endif
+
+void set_chipselect_size(int const cs_size)
+{
+       unsigned int reg;
+       struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+       reg = readl(&iomuxc_regs->gpr[1]);
+
+       switch (cs_size) {
+       case CS0_128:
+               reg &= ~0x7;    /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
+               reg |= 0x5;
+               break;
+       case CS0_64M_CS1_64M:
+               reg &= ~0x3F;   /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
+               reg |= 0x1B;
+               break;
+       case CS0_64M_CS1_32M_CS2_32M:
+               reg &= ~0x1FF;  /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
+               reg |= 0x4B;
+               break;
+       case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
+               reg &= ~0xFFF;  /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
+               reg |= 0x249;
+               break;
+       default:
+               printf("Unknown chip select size: %d\n", cs_size);
+               break;
+       }
+
+       writel(reg, &iomuxc_regs->gpr[1]);
+}

diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index a3cc96f39b2e6c3c3409bbf03518957f9fcf38dd..254136e2288323ed436d8ac1a1fa3a09fe7acc9c 100644 (file)
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -12,3 +12,8 @@
 #define MXC_CPU_MX6Q           0x63
 #define MXC_CPU_MX6D           0x64
 #define MXC_CPU_MX6SOLO                0x65 /* dummy ID */
+
+#define CS0_128                                        0
+#define CS0_64M_CS1_64M                                1
+#define CS0_64M_CS1_32M_CS2_32M                        2
+#define CS0_32M_CS1_32M_CS2_32M_CS3_32M                3

diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 054c680a5a14ec40304aef6876d72fd8081ac16d..f059d0f664b35b4f5630347cdffeb60c56194efb 100644 (file)
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -202,11 +202,6 @@
  */
 #define WBED           1
 
-#define CS0_128                                        0
-#define CS0_64M_CS1_64M                                1
-#define CS0_64M_CS1_32M_CS2_32M                        2
-#define CS0_32M_CS1_32M_CS2_32M_CS3_32M                3
-
 /*
  * CSPI register definitions
  */
@@ -414,8 +409,7 @@ struct weim {
 
 #if defined(CONFIG_MX51)
 struct iomuxc {
-       u32     gpr0;
-       u32     gpr1;
+       u32     gpr[2];
        u32     omux0;
        u32     omux1;
        u32     omux2;
@@ -424,9 +418,7 @@ struct iomuxc {
 };
 #elif defined(CONFIG_MX53)
 struct iomuxc {
-       u32     gpr0;
-       u32     gpr1;
-       u32     gpr2;
+       u32     gpr[3];
        u32     omux0;
        u32     omux1;
        u32     omux2;

diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h
index c35a905141a85deed8d328b374e4d7878093bccf..28ba84415f05b667d24dd329f1a1953189e67a53 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
@@ -26,6 +26,7 @@ u32 get_cpu_rev(void);
 
 const char *get_imx_type(u32 imxtype);
 unsigned imx_ddr_size(void);
+void set_chipselect_size(int const);
 
 /*
  * Initializes on-chip ethernet controllers.